ARMV6 and V7 Supported Features (Windows Embedded CE 6.0)

  • Article

1/5/2010

The ARMV6 and V7 architectures have enhanced cache designs which can improve the performance of the Windows Embedded CE 6.0 kernel. The ARMV6 processor is architecturally similar to the ARMV4I. The ARMV6 can run an OS image targeted for the ARMV4I processor. Both architectures supported direct querying of the processor to determine what features are supported.

Supported features include:

  • Address Space Identifier (ASID) support
    The primary advantage of using the ARMV6 processor is enhanced caching capabilities through ASID support. ASID is used in a Translation Lookaside Buffer (TLB) to differentiate the same virtual address across different processes.
    ASID improves efficient use of the cache and avoids the need for costly flushing and loading of translation buffers on context switches. To accomplish this cached memory is identified using both the VM address and the ASID. Process level debugging is also enhanced since the ASID is also found in the process ID.
  • Branch Target Address Cache (BTAC) flushing enabled
    Flushing the cache is an expensive operation both in terms of CPU performance and in power consumption. BTAC stores recent branch targets in an effort to improve branch prediction.

These features provide a significant saving in software overhead on context switches, avoiding the need to flush on-chip translation buffers in most cases. The result is improved application and operating system performance in battery-powered systems.

See Also

Concepts

ARM Kernels
ARM BSPs
Texas Instruments SDP2420 Development Board Supported Features