OEMARMCacheMode

This function sets the C and B CPU bits to be used to build the ARM page tables. The C and B bits are part of the page table entries and control write-through versus write-back cache mode.

  DWORD OEMARMCacheMode (void);

Return Values

The r0 register (return value) must contain the desired C and B bit configuration. The register can be set to one of the following values:

• ARM_NoBits

  Both C and B bits are cleared.

• ARM_CBit

  The C bit is set.

• ARM_BBit

  The B bit is set.

• ARM_CBBits

  Both the C and B bits are set.

Remarks

The value placed in register r0 must be an immediate data value and not a predefined constant. This function is called at a point in the boot cycle where the memory containing predefined constants has not been initialized yet. Note that C and B bit functionality is processor-specific and different for the ARM720, ARM920, and SA1100. Consult your CPU hardware documentation for the CPU in question before altering these bit configurations. The default configuration (C=B=1) works on all current ARM CPUs and results in the following behavior for the following ARM CPUs:

• ARM720

  Write-through, write-buffer enabled.

• ARM920

  Write-back cache mode.

• SA1100

  Write-back, write-buffer enabled.

Requirements