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Cache Support for Streaming SIMD Extensions 2 Integer Operations

For an explanation of the syntax used in code samples in this topic, see Floating-Point Intrinsics Using Streaming SIMD Extensions.

SSE2 intrinsics use the __m128, __m128i, and __m128d data types, which are not supported on Itanium Processor Family (IPF) processors. Any SSE2 intrinsics that use the __m64 data type are not supported on x64 processors.

The emmintrin.h header file contains the declarations for the SSE2 instructions intrinsics.

void _mm_stream_si128(__m128i *p, __m128i a)

MOVNTDQ

Stores the data in a to the address p without polluting the caches. If the cache line containing address p is already in the cache, the cache will be updated. Address p must be 16-byte aligned.

*p := a

void _mm_stream_si32(int *p, int a)

MOVNTI

Stores the data in a to the address p without polluting the caches. If the cache line containing address p is already in the cache, the cache will be updated.

*p := a

void _mm_clflush(void const*p)

CLFLUSH

Cache line containing p is flushed and invalidated from all caches in the coherency domain.

void _mm_lfence(void)

LFENCE

Guarantees that every load instruction that precedes, in program order, the load fence instruction is globally visible before any load instruction that follows the fence in program order.

void _mm_mfence(void)

MFENCE

Guarantees that every memory access that precedes, in program order, the memory fence instruction is globally visible before any memory instruction that follows the fence in program order.

void _mm_pause(void)

PAUSE

The execution of the next instruction is delayed an implementation specific amount of time. The instruction does not modify the architectural state. This intrinsic provides especially significant performance gain.

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