Feature Detection

To properly identify and use 3DNow! and Enhanced 3DNow! instructions, the application program must determine if the processor supports them. The CPUID instruction gives programmers the ability to determine the instructions supported by a processor. The following provides a summary of the steps needed to determine instruction set support. For a detailed description of the CPUID instruction, see the AMD Processor Recognition Application Note, order number 20734.

  1. Establish that the processor has support for CPUID.

  2. Execute CPUID function 0, which returns the processor vendor string and the highest standard function supported. Save the vendor string for a later comparison. (See step 9.)

  3. If step 2 indicates that the highest standard function is at least 1, execute CPUID function 1, which returns the standard feature flags in the EDX register.

  4. If bit 23 of the standard feature flags is set to 1, MMX technology is supported. MMX instruction support is the basic minimum processor feature required to support other instruction extensions.

  5. Optionally, if bit 25 of the standard feature flags is set, the processor has streaming SIMD extensions (SSE) capabilities. Further qualification of SSE is done by checking for OS support. SSE support might be present in the processor, but not usable due to a lack of OS support for the additional architected registers.

  6. Execute CPUID extended function 8000_0000h. This function returns the highest extended function supported in EAX. If EAX=0, there is no support for extended functions.

  7. If the highest extended function supported is at least 8000_0001h, execute CPUID function 8000_0001h. This function returns the extended feature flags in EDX.

  8. If bit 31 of the extended feature flags is set to 1, the 3DNow! instructions are supported.

  9. If the previously saved vendor string (see step 2) contains "AuthenticAMD", continue on to the next step.

  10. If bit 30 of the extended feature flags is set to 1, the additions to the 3DNow! instruction set are supported.

  11. If bit 22 of the extended feature flags is set to 1, the new multimedia enhancement instructions that augment the MMX instruction set are supported.

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