Registers - vs_5_0

The following input and output registers are implemented in the vertex shader version 5_0.

Input Registers

Register TypeCountR/WDimensionIndexable by r#DefaultsRequires DCL
32-bit Temp (r#)4096(r#+x#[n])R/W4NoNoneYes
32-bit indexable Temp Array (x#[n])4096(r#+x#[n])R/W4YesNoneYes
32-bit input (v#)32R4YesNoneYes
Element in an input resource (t#)128R1NoNoneYes
Sampler (s#)16R1NoNoneYes
ConstantBuffer reference (cb#[index])15R4Yes(contents)NoneYes
iImmediate ConstantBuffer reference (icb[index])1R4Yes(contents)NoneYes

 

Output Registers

Register TypeCountR/WDimensionIndexable by r#DefaultsRequires DCL
NULL (discard result, useful for operations with multiple results)N/AWN/AN/AN/ANo
32-bit output Vertex Data Element (o#)32W4N/AN/AYes

 

Related topics

Shader Model 5

 

 

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