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Registers - vs_3_0

This section contains reference information for the input and output registers implemented by vertex shader version 3_0.

Input Registers

RegisterNameCountR/W# Read ports# Reads / instDimensionRelAddrDefaultsRequires DCL
v# Input Register 16R1Unlimited4a0/aLSee note 1Yes
r# Temporary Register 32R/W3Unlimited4NoNoneNo
c# Constant Float Register See note 2R1Unlimited4a0/aL(0, 0, 0, 0)No
a0 Address Register 1R/W1Unlimited4NoNoneNo
b# Constant Boolean Register 16R111NoFALSENo
i# Constant Integer Register 16R114No(0, 0, 0, 0)No
aL Loop Counter Register 1R1Unlimited1NoNoneNo
p0 Predicate Register 1R/W114nononeno
s# Sampler (Direct3D 9 asm-vs) 4R114NoSee note 3Yes

 

Notes:

  1. Partial (0, 0, 0, 1) - If only a subset of channels are updated, the remaining channels will default to (0, 0, 0, 1).
  2. Equal to D3DCAPS9.MaxVertexShaderConst (at least 256 for vs_3_0).
  3. Defaults for sampler lookup exist, but values depend on texture format.

Output Registers

Output registers have been collapsed into 12 o# (output) registers. These can be used for anything the user wants to interpolate for the pixel shader: texture coordinates, colors, fog, etc.

RegisterNameCountR/WDimensionRelAddrDefaultsRequires DCL
o#Output Register12W4aLNoneYes

 

Related topics

Vertex Shader Registers

 

 

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