OEMARMCacheMode (Windows CE 5.0)
This function sets the cache mode used to build the ARM CPU page tables. For example, the C and B bits are part of the page table entries and control write-through versus write-back cache mode.
DWORD OEMARMCacheMode (void);
The r0 register, which contains the return value, must contain the desired C and B bit configuration.
The register can be set to one of the following values.
|ARM_NoBits||Both C and B bits are cleared.|
|ARM_CBit||The C bit is set.|
|ARM_BBit||The B bit is set.|
|ARM_CBBits||Both C and B bits are set.|
The value placed in register r0 must be an immediate data value and not a predefined constant. This function is called at a point in the boot cycle when the memory containing predefined constants has not been initialized yet.
C and B bit functionality is processor-specific and different for the ARM720, ARM920, and SA1100 processors. Before altering these bit configurations, consult your CPU hardware documentation before altering these bit configurations.
The default configuration (C = B = 1) works on all current ARM CPUs.
Windows CE supports the ability to set any cache mode bits, not just C and B bits.
The following table shows the behavior for ARM CPUs.
|ARM720||Write-through, write-buffer enabled|
|ARM920||Write-back cache mode|
|SA1100||Write-back, write-buffer enabled|
OS Versions: Windows CE 3.0 and later.
Link Library: Nk.lib.
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