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OEMARMCacheMode

OEMARMCacheMode (Windows CE 5.0)

Windows CE 5.0
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This function sets the cache mode used to build the ARM CPU page tables. For example, the C and B bits are part of the page table entries and control write-through versus write-back cache mode.

DWORD OEMARMCacheMode (void);

Parameters

None.

Return Values

The r0 register, which contains the return value, must contain the desired C and B bit configuration.

The register can be set to one of the following values.

ValueDescription
ARM_NoBitsBoth C and B bits are cleared.
ARM_CBitThe C bit is set.
ARM_BBitThe B bit is set.
ARM_CBBitsBoth C and B bits are set.

Remarks

The value placed in register r0 must be an immediate data value and not a predefined constant. This function is called at a point in the boot cycle when the memory containing predefined constants has not been initialized yet.

C and B bit functionality is processor-specific and different for the ARM720, ARM920, and SA1100 processors. Before altering these bit configurations, consult your CPU hardware documentation before altering these bit configurations.

The default configuration (C = B = 1) works on all current ARM CPUs.

Windows CE supports the ability to set any cache mode bits, not just C and B bits.

The following table shows the behavior for ARM CPUs.

ARM CPUBehavior
ARM720Write-through, write-buffer enabled
ARM920Write-back cache mode
SA1100Write-back, write-buffer enabled

Requirements

OS Versions: Windows CE 3.0 and later.
Header: Mem_arm.h.
Link Library: Nk.lib.

See Also

How to Develop an OEM Adaptation Layer


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