Export (0) Print
Expand All

OEMCacheRangeFlush (Compact 2013)

10/16/2014

This function flushes or invalidates a certain range of the cache or translation look-aside buffer (TLB).


void OEMCacheRangeFlush(
  LPVOID pAddr,
  DWORD dwLength,
  DWORD dwFlags 
);

pAddr

[in] Starting virtual address where the cache operation is to be performed. The cache operation is specified by the value in the dwFlags parameter.

dwLength

[in] Specifies the length, in bytes.

dwFlags

[in] Specifies the operations to be performed.

The following tables shows possible values.

Value

Description

CACHE_SYNC_WRITEBACK

Write back cached data.

CACHE_SYNC_DISCARD

Write back and discard cached data.

CACHE_SYNC_INSTRUCTIONS

Discard all cached instructions.

CACHE_SYNC_FLUSH_I_TLB

Flush the instruction TLB.

CACHE_SYNC_FLUSH_D_TLB

Flush the data TLB.

CACHE_SYNC_FLUSH_TLB

Flush both the instruction and data TLBs.

CACHE_SYNC_L2_WRITEBACK

Write back the L2 cache.

CACHE_SYNC_L2_DISCARD

Write back and discard the L2 cache.

CACHE_SYNC_ALL

Perform all of the above operations.

CSF_PROCESS_SWITCH

Process switch.

CSF_PROCESS_EXIT

Process exit.

CSF_VM_CHANGE

VM change.

CSF_LOADER

Code loading.

CSF_EXTERNAL

External call.

CSF_OBJSTORE

Not used.

CSF_DRAIN_WRITE_BUFFER_ONLY

Note used.

CSF_CURR_CPU_ONLY

Flush local CPU only.

The kernel calls this function. OEMs must implement this function in the OAL. This function replaces calls to FlushDCache, FlushICache, and TLBClear.

If pAddr is set to NULL and dwLength is set to zero, this means all addresses. For example, the call OEMCacheRangeFlush(NULL, 0, CACHE_SYNC_FLUSH_TLB) flushes the data in the TLB. OEMCacheRangeFlush(NULL, 0, CACHE_SYNC_DISCARD) writes back and discards everything in the data cache.

If no CSF_XXX flag is specified, the cache is flushed for coherency.

Operations can also be combined. For example, the call OEMCacheRangeFlush(NULL, 0, CACHE_SYNC_FLUSH_TLB | CACHE_SYNC_DISCARD | CACHE_SYNC_INSTRUCTIONS) writes back and discards the entire data cache, invalidates the entire instruction cache, and flushes the instruction and data TLBs.

If the memory management unit (MMU) supports probing, the special case where dwLength==PAGE_SIZE might be useful because it is commonly used when paging code.

In general, if you are implementing this function you should perform TLB flushes at the end of the function. For example, if dwFlags==(CACHE_SYNC_DISCARD|CACHE_SYNC_FLUSH_TLB), the cache discard operation is usually performed before the TLB flush.

Depending on cache management design of the hardware, flushing the L1 cache may require flushing the L2 cache. BSP developer should follow guidance from hardware vendor to implement L1 and L2 cache flush logic.

Header

Developer Implemented

Library

Developer Implemented

Show:
© 2015 Microsoft