Registers - vs_2_0

This section contains reference information for the input and output registers implemented by vertex shader version 2_0.

Input Registers

RegisterNameCountR/W# Read ports# Reads / instDimensionRelAddrDefaultsRequires DCL
v# Input Register 16R1Unlimited4NoSee note 1Yes
r# Temporary Register 12R/W3Unlimited4NoNoneNo
c# Constant Float Register See note 2R124a0 / aL(0, 0, 0, 0)No
a0 Address Register 1R/W124NoNoneNo
b# Constant Boolean Register 16R111NoFALSENo
i# Constant Integer Register 16R114No(0, 0, 0, 0)No
aL Loop Counter Register 1R121NoNoneNo



  1. Partial (0, 0, 0, 1) - If only a subset of channels are updated, the remaining channels will default to (0, 0, 0, 1).
  2. Equal to D3DCAPS9.MaxVertexShaderConst (at least 256 for vs_2_0).

Output Registers

RegisterNameCountR/WDimensionRelAddrDefaultsRequires DCL
oPos Position Register 1W4NoNoneNo
oFog Fog Register 1W1NoNoneNo
oPts Point Size Register 1W1NoNoneNo
oD# Color Register; See note 12W4NoNoneNo
oT# Texture Coordinate Register 8W4NoNoneNo



  • oD0 is the diffuse color output; oD1 is the specular color output.

Related topics

Vertex Shader Registers