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Predicate Register (HLSL VS reference)

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This vertex shader output register contains a per-channel Boolean value.

A predicate register is supported by the following versions.

Vertex shader versions 1_1 2_0 2_sw 2_x 3_0 3_sw
predicate register x x x

 

Here are the register properties.

Register type Count R/W # Read ports # Reads/inst Dimension RelAddr Defaults Requires DCL
Predicate(p) 1 R/W 1 1 4 N/A None N

 

The predicate register can be modified with setp_comp - vs. There are no default values for this register, an application needs to set the register before it is used.

Vertex Shader Registers