/arch (Minimum CPU Architecture)
Collapse the table of content
Expand the table of content
The document is archived and information here might be outdated

/arch (Minimum CPU Architecture)

Specifies the architecture for code generation using the Streaming SIMD Extensions (SSE) and Streaming SIMD Extensions 2 (SSE2) instructions.



/arch is only available when compiling for the x86 platform. This compiler option is not available when compiling for x64 or Itanium.

The SSE instructions exist in various Pentium and AMD Athlon processors. The SSE2 instructions only exist on the Pentium 4 processor.

/arch:SSE allows the compiler to use the SSE instructions, and /arch:SSE2 allows the compiler to use the SSE2 instructions.

_M_IX86_FP indicates which, if any, /arch compiler option was used; see Predefined Macros for more information.

The optimizer will choose when and how to make use of the SSE and SSE2 instructions when /arch is specified. SSE and SSE2 instructions will be used for some scalar floating-point computations, when it is determined that it is faster to use the SSE/SSE2 instructions and registers rather than the x87 floating-point register stack. As a result, your code will actually use a mixture of both x87 and SSE/SSE2 for floating-point computations. Additionally, with /arch:SSE2, SSE2 instructions can be used for some 64-bit integer operations.

In addition to using the SSE and SSE2 instructions, the compiler will also use other instructions that are present on the processor revisions that support SSE and SSE2. An example is the CMOV instruction that first appeared in the Pentium Pro revision of the Intel processors.

When compiling with /clr (Common Language Runtime Compilation), /arch will have no effect on code generation for managed functions. /arch only affects code generation for native functions.

/arch and /QIfist (Suppress _ftol) can not be used on the same compiland.

In particular, if the user does not use _controlfp to modify the FP control word, then the run-time startup code will set the x87 FPU control word precision-control field to 53-bits, so all float and double operations within an expression will occur with 53-bit significand and 15-bit exponent. All SSE single-precision operations will, however, use a 24-bit significand/8-bit exponent, and SSE2 double-precision operations will use a 53-bit significand/11-bit exponent. For more information, see _control87, _controlfp, __control87_2.

To illustrate, these differences are possible within a single expression tree, not in cases where there is a user assignment involved after each subexpression:

r = f1 * f2 + d;  // Different results are possible on SSE/SSE2.


   t = f1 * f2;   // Do f1 * f2, round to the type of t.
   r = t + d;     // This should produce the same overall result 
                  // regardless whether x87 stack or SSE/SSE2 is used.

controlfp does not change the MXCSR control bits, so with /arch:SSE2, any functionality that depends on using controlfp will be broken.

To set this compiler option in the Visual Studio development environment

  1. Open the project's Property Pages dialog box. For details, see How to: Open Project Property Pages.

  2. Click the C/C++ folder.

  3. Click the Code Generation property page.

  4. Modify the Enable Enhanced Instruction Set property.

To set this compiler option programmatically

© 2016 Microsoft