Watchdog Timer Hardware Requirements for Windows
Updated: August 28, 2006
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Watchdog Timer Hardware Requirements Microsoft Windows Server 2003 is for engineers who are designing watchdog timer hardware that will operate with the Microsoft Windows Server 2003 operating system.
Conventions Used in This Specification
The following conventional terms are used throughout this specification.
Windows Server 2003
Required, Recommended, and Optional Features
In this specification, features are described as Required or Recommended as follows:
Required. These basic hardware features must be implemented to comply with this hardware reference specification.
Recommended. These features add functionality supported by Windows Server 2003 but are not required for compliance with this hardware reference specification.
References and Resources
The following lists some of the information resources, services, and tools available to help build hardware that meets the requirements defined in this specification. This section also lists references for documents referred to in this specification.
Information Resources from Microsoft
Microsoft Developer Network (MSDN) Professional Subscription
Microsoft Windows Platform Development
Microsoft Windows Hardware Quality Labs (WHQL)
Advanced Configuration and Power Interface Specification
Microsoft Windows DDK and Platform SDK
Provided with MSDN Professional Subscription
Microsoft Windows Hardware Compatibility List (HCL)
Watchdog Timer Requirements
This section defines specific requirements for watchdog timer capabilities provided in a Windows Server 2003 appliance.
1. Server system includes hardware watchdog timer
2. Watchdog timer hardware meets requirements, if present
2.1 Operating States. The watchdog timer hardware must support two main operating states, Disabled and Enabled:
In the Disabled state, the countdown must be stopped and cannot be started by the operating system.
In the Enabled state, the watchdog timer must support two sub-states, Running and Stopped:
All states must be visible to the operating system.
2.2 Enabled/Disabled Transition Mechanism. A mechanism for transitioning between the Enabled and Disabled states must be provided. This mechanism must be independent of the operating system, for example, using either a hardware jumper or a BIOS configuration setting.
2.3 Stopped/Running Transition Mechanism. The watchdog timer hardware must provide to the operating system a mechanism for transitioning the hardware between the Enabled\Stopped and Enabled\Running states.
2.4 Initial Enabled Sub-state Configuration Mechanism. [Recommended] A mechanism should be provided for configuring the initial Enabled\Stopped or Enabled\Running sub-state. If provided, the mechanism must be configurable using the BIOS setup. If not provided and the watchdog is enabled, the initial configuration must be set to the Enabled\Stopped sub-state.
It is highly recommended that systems provide this mechanism to protect against boot failures. If this mechanism is not provided the system will not be able to automatically recover should a system hang occur before the operating system enables the watchdog timer driver.
Note: When configured to start in the Enabled\Running state, the BIOS must not trigger the watchdog to begin counting until immediately before the BIOS turns control over to the operating system or, in the case of a network boot, to the PXE boot code.
2.5 Initial Countdown Time Interval Configuration Mechanism. [Recommended] A mechanism for configuring the initial countdown time should be provided that can be configured using the BIOS setup.
Note: When the system is powered on, the watchdogs default countdown time interval should be set to a value greater than 2 minutes + 2*Tb, where Tb is the time from when the watchdog is started until the Master Boot Record is executed from the disk. This affords enough time for the operating system to boot and take control of the watchdog timer hardware.
2.6 Countdown Time Range Configuration Method. The watchdog timers hardware must provide the operating system a method for setting the countdown time to a range of values from 1 second to 511 seconds, with a granularity of one second. This allows the operating system to shut down or restart without possibility of a watchdog reset during shut down. A wider range of countdown values is allowed, from 1 ms to 65,535 seconds.
2.7 Shutdown/Restart Request Mechanism. The watchdog timer hardware must provide a mechanism for the operating system to request to either shut down or restart the machine upon the countdown reaching zero. Shutdown is equivalent to a power off by holding the power button for > 4 seconds. Restart is equivalent to a system reset (that is, pressing the reset button).
2.8 Watchdog Fired Bit. The watchdog timer hardware must provide a bit that indicates that the current restart was caused by the watchdog timer counter reaching zero. The operating system must be able to read and write to this bit. The bit is cleared by a power cycle or by the operating system and must remain cleared on any restart that is not triggered by the watchdog expiring.
2.9 Counter Restart after POST. If the timer is configured to be enabled and running at system boot, the watchdog timer counter must be triggered after the BIOS POST to ensure that the operating system has time to load and boot before the counter reaches zero.
2.10 Control/Status Register. The timer must provide a control/status register that conforms to the format in the following table.
Watchdog Control/Status Register (32 bits)
2.11 Count Register. The timer must provide a count register that conforms to the format in the following table.
Watchdog Count Register (32 bits)
2.12 Write Complete. Writes to the registers must complete in a single bus clock cycle to avoid race conditions.
3. Watchdog timer firmware meets requirements, if present
Watchdog Resource Table (WDRT)