FAQ for PCI and PCIe Issues for “Designed for Windows” Logo

Updated: May 17, 2004

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  Interrupt Disable Required for "Designed for Windows" Logo
  PCI Express Isochronous “Designed for Windows” Logo Requirements

Interrupt Disable Required for "Designed for Windows" Logo

August 8, 2002

Microsoft Online Crash Analysis (OCA) and internal bug report data show that interrupt storms caused by faulty drivers affect system reliability and cause a significant number of system hangs. The Interrupt Disable bit specified in PCI Local Bus Specification Revision 2.3 provides a mechanism for handling interrupt storms. When Interrupt Disable is set for a device or function, it will stop asserting INTx# during runtime.

The Interrupt Disable bit and corresponding Interrupt Status bit were added to PCI Local Bus Specification Revision 2.3, released on March 29, 2002. The PCI SIG required compliance with Revision 2.3 no later than January 1, 2004. Implementation of Interrupt Disable became a Windows Logo Program requirement on January 1, 2004. Operating system control of these bits is planned for a future release of Microsoft Windows.

For more information about Interrupt Disable and Interrupt Status, see section 6.2 of the PCI Local Bus Specification Revision 2.3: http://www.pcisig.com/specifications/ 

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PCI Express Isochronous “Designed for Windows” Logo Requirements

May 17, 2004

PCI Express Isochronous DMA (Isoch) is the utilization of the extended virtual channel mechanism to provide bandwidth and latency guarantees. Isoch is an optional feature of PCI Express. Chipset vendors and IHVs can choose to implement Isoch at their discretion.

PCI Express Base Specification V1.0a does not provide guidelines around the rules and guarantees of Isoch implementation. Chipset vendors and IHVs are developing different, incompatible Isoch implementations.

• Some chipset vendors are choosing not to implement Isoch.

  • Isoch is optional; chipsets not required to have it.

  • Isoch-dependent adapters will not run on these systems.

• Some chipset vendors are implementing Isoch using non-snoop DMA.

  • Non-snoop Isoch is used to meet bit rate and latency needs while minimizing buffer sizes.

  • Isoch guarantees will break if snooping of the CPU cache on the front side bus causes DMA transfers to be delayed.

Risks

• Risks of incompatible Isoch hardware:

  • Isoch adapters fail in unpredictable ways in non-Isoch systems.

  • Isoch adapters and Isoch systems that do not agree on the “rules” and “guarantees” of Isochrony perform poorly together.

• Risks of Non-Snoop Isoch DMA:

  • If memory and cache are not kept coherent by the hardware, non-snoop Isoch can cause driver programming, debugging, and support to become very difficult.

  • If DMA buffers need to be mapped uncached/write-combine, this can introduce buffer performance and management issues.

Effects

• It is difficult for users to determine Isoch hardware compatibility. This creates an additional support burden for Microsoft and its partners, and it creates a poor user experience if Isoch-dependent adapters fail.

• The proliferation of implementations based on the non-snoop Isoch approach introduces long-term reliability and performance risks.

  • Microsoft had seen similar problems in Windows and Windows CE on non-snoop RISC CPU architectures.

  • Non-snoop Isoch increases the complexity of driver development. Consequently, driver quality will go down, resulting in increasing Windows crashes.

  • There are related increases in development, support, and educational costs.

What Microsoft Is Doing

• Microsoft will discuss the long-term direction of PCI Express Isoch with chipset vendors and IHVs.

• “Designed for Windows” logo requirements have been added for PCI Express Isochronous in both Windows Logo Program Requirements (WLP) 2.2 and 3.0.

• Until proven compatible and safe, Isoch implementations will not be allowed in the “Designed for Windows” logo program for hardware.

• High Definition (HD) Audio devices are exempt from Isoch "Designed for Windows" requirements.

  • HD Audio is a chipset integrated device. Microsoft has reviewed HD Audio Isoch usage model and determined that it is safe.

  • Microsoft is providing an HD Audio Controller driver with proper buffer management to eliminate risks.

PCI Express Isochronous “Designed for Windows” Requirements

• PCI Express System BIOS Requirements:

  • A1.1.4.19 System BIOS disables the extended (non-VC0) virtual channel(s) in the PCI Express devices.
    The system BIOS sets the virtual channel (VC) Enable bit (PCI Express Base Specification V1.0a, Section 7.11.7, VC Resource Control Register: bit 31) to 0 for all extended (non-VC0) virtual channels in all PCI Express devices. PCI Express High Definition Audio Controllers, which use class code 04 and subclass code 03, are exempt from this requirement. Because extended support for virtual channel hardware is optional, this requirement addresses the scenario where incompatible virtual channel hardware implementations might cause system reliability, stability, and performance issues. Hardware vendors are encouraged to work with Microsoft to define the future direction of extended virtual channel support.

• PCI Express Driver Requirement:

  • B2.7.4.2 Device driver for PCI Express device must not modify No Snoop or VC Enable settings. The device driver must not modify either the "Enable No Snoop" bit (PCI Express Base Specification V1.0a, Section 7.8.4, Device Control Register: bit 11) for the device or the "VC Enable" bit (PCI Express Base Specification V1.0a, Section 7.11.7, VC Resource Control Register: bit 31) for any of the device’s extended (non-VC0) virtual channel or channels.

• PCI Express Support e-mail: pciesup@microsoft.com

For up-to-date information about requirements, see FAQ for Windows Logo Program for Hardware.

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