IRP
MDL
Expand Minimize

PCI_COMMON_CONFIG structure

The PCI_COMMON_CONFIG structure is obsolete. It defines standard PCI configuration information returned by the obsolete HalGetBusData or HalGetBusDataByOffset routine for the input BusDataType PCIConfiguration, assuming the caller-allocated Buffer is of sufficient Length.

Syntax


typedef struct _PCI_COMMON_CONFIG {
  USHORT VendorID;
  USHORT DeviceID;
  USHORT Command;
  USHORT Status;
  UCHAR  RevisionID;
  UCHAR  ProgIf;
  UCHAR  SubClass;
  UCHAR  BaseClass;
  UCHAR  CacheLineSize;
  UCHAR  LatencyTimer;
  UCHAR  HeaderType;
  UCHAR  BIST;
  union {
    struct {
      ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];
      ULONG Reserved1[2];
      ULONG ROMBaseAddress;
      ULONG Reserved2[2];
      UCHAR InterruptLine;
      UCHAR InterruptPin;
      UCHAR MinimumGrant;
      UCHAR MaximumLatency;
    } type0;
  } u;
  UCHAR  DeviceSpecific[192];
} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;

Members

VendorID

Identifies the manufacturer of the device. This must be a value allocated by the PCI SIG.

DeviceID

Identifies the particular device. This value is assigned by the manufacturer.

Command

Accesses the PCI device's control register. Writing a zero to this register renders the device logically disconnected from the PCI bus except for configuration access. Otherwise, the functionality of the register is device-dependent. Possible system-defined bit encodings for this member include:

PCI_ENABLE_IO_SPACE

PCI_ENABLE_MEMORY_SPACE

PCI_ENABLE_BUS_MASTER

PCI_ENABLE_SPECIAL_CYCLES

PCI_ENABLE_WRITE_AND_VALIDATE

PCI_ENABLE_VGA_COMPATIBLE_PALETTE

PCI_ENABLE_PARITY

PCI_ENABLE_WAIT_CYCLE

PCI_ENABLE_SERR

PCI_ENABLE_FAST_BACK_TO_BACK

Status

Accesses the PCI device's status register. The functionality of this register is device-dependent. Possible system-defined bit encodings for this member include:

PCI_STATUS_FAST_BACK_TO_BACK // read-only

PCI_STATUS_DATA_PARITY_DETECTED

PCI_STATUS_DEVSEL // 2 bits wide

PCI_STATUS_SIGNALED_TARGET_ABORT

PCI_STATUS_RECEIVED_TARGET_ABORT

PCI_STATUS_RECEIVED_MASTER_ABORT

PCI_STATUS_SIGNALED_SYSTEM_ERROR

PCI_STATUS_DETECTED_PARITY_ERROR

RevisionID

Specifies the revision level of the device described by the DeviceID member. This value is assigned by the manufacturer.

ProgIf

Identifies the register-level programming interface, if any, for the device, according to the PCI classification scheme.

SubClass

Identifies the subtype, if any, of the device, according to the PCI classification scheme.

BaseClass

Identifies type of the device, according to the PCI classification scheme.

CacheLineSize

Contains the system cache line size in 32-bit units. This member is relevant only for PCI bus-master devices. The system determines this value during the boot process.

LatencyTimer

Contains the value of the latency timer in units of PCI bus clocks. This member is relevant only for PCI bus-master devices. The system determines this value during the boot process.

HeaderType

The system ORs the value of this member with PCI_MULTIFUNCTION, if appropriate to the device. The value of this member indicates the PCI_HEADER_TYPE_0 layout that follows.

BIST

Zero indicates that the device does not support built-in self-test. Otherwise, the device supports built-in self-test according to the PCI standard.

u
type0

Drivers call HalAssignSlotResources to configure these values and to get back the bus-relative values passed to other configuration routines.

BaseAddresses

Base addresses.

Reserved1

Reserved.

ROMBaseAddress

ROM base address.

Reserved2

Reserved.

InterruptLine

Interrupt line number.

InterruptPin

Interrupt pin number.

MinimumGrant

Minimum grant.

MaximumLatency

Maximum latency.

DeviceSpecific

Contains any device-specific initialization information that is available.

Remarks

Certain members of this structure have read-only values, so attempts to reset them are ignored. These members include the following: VendorID, DeviceID, RevisionID, ProgIf, SubClass, BaseClass, HeaderType, InterruptPin, MinimumGrant, and MaximumLatency.

Other members are provisionally read-only: that is, the system initializes them to their correct values, so drivers can safely treat them as read-only. However, they can be reset if a bus-master driver finds it necessary. These members include the following: CacheLineSize and LatencyTimer.

Requirements

Header

Wdm.h (include Wdm.h, Ntddk.h, or Ntifs.h)

See also

HalAssignSlotResources
HalGetBusData
HalGetBusDataByOffset
HalSetBusData
HalSetBusDataByOffset

 

 

Send comments about this topic to Microsoft

Show:
© 2014 Microsoft