Hypervisor Virtual MMU
Virtual processors expose virtual memory and a translation look-aside buffer (TLB), which caches translations from virtual addresses to (guest) physical addresses. As with the TLB on a logical processor, the virtual TLB is a non-coherent cache, and this non-coherence is accessible to guests. The hypervisor exposes operations to flush the TLB. Guests can use these operations to remove potentially inconsistent entries and make virtual address translations predictable.
The following sections describe the hypervisor's implementation of virtual MMU:
Build date: 11/16/2013