Registers - cs_5_0

The following input and output registers are implemented in the compute shader version 5_0.

Input Registers

Register TypeCountR/WDimensionIndexable by r#DefaultsRequires DCL
32-bit Temp (r#) 4096(r#+x#[n])R/W4NoNoneYes
32-bit Indexable Temp Array (x#[n])4096(r#+x#[n])R/W4YesNoneYes
32-bit Thread Group Shared Memory (g#[n]) 8192 (sum of all shared memory decls for thread group) R/W1 (can be declared various ways) YesNoneYes
Element in an input resource (t#) 128R1NoNoneYes
Sampler (s#) 16R1NoNoneYes
ConstantBuffer reference (cb#[index]) 15R4Yes (contents)NoneYes
Immediate ConstantBuffer reference (icb[index]) 1R4Yes(contents)NoneYes
ThreadID (vThreadID.xyz) 1R3NoN/AYes
ThreadGroupID (vThreadGroupID.xyz) 1R3NoN/AYes
ThreadIDInGroup (vThreadIDInGroup.xyz) 1R3NoN/AYes
ThreadIDInGroupFlattened (vThreadIDInGroupFlattened) 1R1NoN/AYes

 

Output Registers

Register TypeCountR/WDimensionIndexable by r#DefaultsRequires DCL
NULL (discard result, useful for ops with multiple results) N/AWN/AN/AN/ANo
Unordered Access View (u#) 8R/W1NoNoYes

 

 

 

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