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Registers - ds_5_0

The following input and output registers are implemented in the domain shader version 5_0.

Input Registers

Register TypeCountR/WDimensionIndexable by r#DefaultsRequires DCL
32-bit Temp (r#)4096(r#+x#[n])R/W4NoNoneYes
32-bit indexable Temp Array (x#[n])4096(r#+x#[n])R/W4YesNoneYes
32-bit Input Control Points (vcp[vertex][element])32 See note 1 below.R4(component)*32(element)*32(vert)YesNoneYes
32-bit Input Patch Constants (vpc[vertex])32 See note 2 below.R4YesNoneYes
32-bit input location in domain (vDomain.xy, vDomain.xyz))1R3NoN/AYes
32-bit UINT Input PrimitiveID (vPrim)1R1NoN/AYes
Element in an input resource (t#)128R128YesNoneYes
Sampler (s#)16R1YesNoneYes
iConstantBuffer reference (cb#[index])15R4YesNoneYes
iImmediate ConstantBuffer reference (icb[index])1R4Yes(contents)NoneYes

 

Note 1: The domain shader sees the hull shader outputs in 2 separate sets of registers. The vcp registers can see all of the hull shader’s output Control Points. The vpc registers can see all of the hull shader’s Patch Constant output data.

Note 2: Because code for hull shader Patch Constant Fork or Join Phases output TessFactors using names such as SV_TessFactor, the domain shader must match those declarations on the equivalent vpc input if it wishes to see those values.

Output Registers

Register TypeCountR/WDimensionIndexable by r#DefaultsRequires DCL
32-bit output Vertex Data Element (o#)32W4YesNoneYes

 

 

 

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