Hypervisor Virtual Processor Execution
The virtual machine interface that is exposed by each partition exposes virtual processors that are specific to particular architectures. This section specifies the core CPU aspects of virtual processors. The Hypervisor Virtual MMU and Caching and Hypervisor Virtual Interrupt Control sections specify the memory management unit (MMU) and interrupt controller aspects of virtual processors.
A complete definition of virtual processor behavior requires hundreds of pages of CPU manuals. The following sections specify the behavior of virtual processors by referencing processor manuals for physical x64 processors and by discussing only cases where a virtual processor's behavior differs from that of a logical processor; that is, the baseline behavior of a virtual processor is defined by the Intel and AMD processor reference manuals.
Some differences exist between AMD's and Intel's implementations. These differences, which are visible to guests, might include the following items. Note that this list is not comprehensive and is likely to change as newer generations of processors are released:
- Intel processors support:
- SSE3 instruction
- AMD processors support:
- 3DNow! instructions
- Fast FXSAVE mechanism
- Additional MMX extensions
- PREFETCHW instruction
- SAHF and LAHF instructions in long mode
The following sections specify the core CPU aspects of virtual processors:
Build date: 10/26/2012