An operation has acquire semantics if other processors will always see its effect before any subsequent operation's effect. An operation has release semantics if other processors will see every preceding operation's effect before the effect of the operation itself.

Consider the following code example:

  a++;
  b++;
  c++;

From another processor's point of view, the preceding operations can appear to occur in any order. For example, the other processor might see the increment of b before the increment of a.

Atomic operations, such as those that the InterlockedXxx routines perform, have both acquire and release semantics by default. However, Itanium-based processors execute operations that have only acquire or only release semantics faster than those that have both. Therefore, the system provides InterlockedXxxAcquire and InterlockedXxxRelease versions of some of the InterlockedXxx routines.

For example, the InterlockedIncrementAcquire routine uses acquire semantics to increment a variable. If you rewrote the preceding code example as follows:

  InterlockedIncrementAcquire(&a);
  b++;
  c++;

other processors would always see the increment of a before the increments of b and c.

Likewise, the InterlockedIncrementRelease routine uses release semantics to increment a variable. If you rewrote the code example once again, as follows:

  a++;
  b++;
  InterlockedIncrementRelease(&c);

other processors would always see the increments of a and b before the increment of c.

If the processor does not provide instructions that have only acquire or only release semantics, the system will use the corresponding routine that provides both types of semantics. For example, on x86 processors both InterlockedIncrementAcquire and InterlockedIncrementRelease are equivalent to InterlockedIncrement.

The following table lists the routines that have acquire-only and release-only variants.