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Register Set

The multimedia units in the processor combine the existing MMX instructions with the new 3DNow! instructions. In addition, by merging 3DNow! with MMX, it becomes possible to write x86 programs containing integer, MMX, and floating-point graphics instructions with no performance penalty for switching between the multimedia (integer) and 3DNow! (floating-point) units.

The processor implements eight 64-bit 3DNow!/MMX registers. These registers are mapped onto the floating-point registers. As shown in the following figure, the 3DNow! and MMX instructions refer to these registers as MM0 to MM7. Mapping the new 3DNow!/MMX registers onto the floating-point register stack enables backwards compatibility for the register saving that must occur as a result of task switching.

3DNow!/MMX Registers

3DNow! MMX registers

Aliasing the 3DNow!/MMX registers onto the floating-point register stack helps provide an excellent method to introduce 3DNow! and MMX technology, because it does not require modification to existing operating systems. Instead of requiring operating system modifications, new 3DNow! and MMX technology applications are supported through device drivers, 3DNow! and MMX libraries, or dynamic-link library (DLL) files.

Current operating systems have support for floating-point operations and the floating-point register state. Using the floating-point registers for 3DNow! and MMX code is a convenient way of implementing nonintrusive support for 3DNow! and MMX instructions. Every time the processor executes a 3DNow! or MMX instruction, all floating-point register tag bits are set to zero (00b=valid), except for the FEMMS and EMMS instructions, which set all tag bits to one (11b=empty).

Executing the PREFETCH instruction does not change the tag bits.

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