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Compiler Support for the MMX, SSE, and SSE2 Intrinsics

To support the use of MMX, SSE, and SSE2 intrinsics, the compiler includes the following features:

  • Data alignment

  • Inline assembly

Previously, alignment issues in programs were addressed either by the compiler or directly in hardware. Also, any alignment changes needed for a program to run correctly were automatically enabled. However, with the advent of intrinsic support, the user must take a more active role to guarantee that alignment issues are appropriately addressed.

Many of the new intrinsics have data alignment requirements. If these intrinsics are used and data is not appropriately aligned, the program will throw an exception that must be handled by the program; otherwise, the program will fault.

The new intrinsics require aligned data to allow better performance. With the size of new registers implemented to support the new, enhanced instruction sets, new alignment requirements were defined to make the best use of recent cache architectures. Specific alignment requirements for each intrinsic can be found in the documentation for the intrinsic.

There are different tools to specify appropriate rules for the alignment of data. For alignment of user declared variables, for example, static or automatic data, refer to the align section documentation. For data dynamically allocated from the heap, refer to the data alignment functions.

NoteNote

The __m64, __m128, __m128i and __m128d new data types already have an alignment value.

The compiler supports use of intrinsic assembly instructions in inline assembly (__asm) blocks. The compiler also accepts the new syntax MMWORD PTR and XMMWORD PTR to refer to 64- and 128-bit data.

For information on how to detect the capabilities of a CPU, see CPUID sample.

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