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/arch (Minimum CPU Architecture)

Specifies the architecture for code generation by using the Streaming SIMD Extensions (SSE), Streaming SIMD Extensions 2 (SSE2), and Advanced Vector Extension (AVX) instructions.

/arch:[SSE|SSE2|AVX]
NoteNote

/arch:SSE and /arch:SSE2 are only available when you compile for the x86 platform. /arch:AVX is only available for the x86 and x64 platforms. This compiler option is not available when you compile for Itanium.

The SSE and SSE2 instructions exist on various Intel and AMD processors. The AVX instructions exist on Intel Sandy Bridge processors and AMD Bulldozer processors.

/arch:SSE enables the compiler to use the SSE instructions. /arch:SSE2 enables the compiler to use the SSE2 instructions. /arch:AVX directs the compiler to use the AVX instruction encodings.

_M_IX86_FP indicates which, if any, /arch compiler option was used. For more information, see Predefined Macros.

The optimizer chooses when and how to use the SSE and SSE2 instructions when /arch is specified. SSE and SSE2 instructions are used for some scalar floating-point computations, when it is determined that it is faster to use the SSE/SSE2 instructions and registers instead of the x87 floating-point register stack. As a result, your code will actually use a mixture of both x87 and SSE/SSE2 for floating-point computations. Additionally, with /arch:SSE2, SSE2 instructions can be used for some 64-bit integer operations.

In addition to using the SSE and SSE2 instructions, the compiler also uses other instructions that are present on the processor revisions that support SSE and SSE2. An example is the CMOV instruction that first appeared on the Pentium Pro revision of the Intel processors.

When you compile by using /clr, /arch has no effect on code generation for managed functions. /arch only affects code generation for native functions.

/arch and /QIfist cannot be used on the same compiland.

In particular, if the user does not use _controlfp to modify the FP control word, then the run-time startup code will set the x87 FPU control word precision-control field to 53-bits. Therefore, every float and double operation in an expression occurs with a 53-bit significand and a 15-bit exponent. However, every SSE single-precision operation uses a 24-bit significand/8-bit exponent, and SSE2 double-precision operations use a 53-bit significand/11-bit exponent. For more information, see _control87, _controlfp, __control87_2.

These differences are possible in one expression tree, but not in cases where a user assignment is involved after each subexpression.

r = f1 * f2 + d;  // Different results are possible on SSE/SSE2.

Against:

   t = f1 * f2;   // Do f1 * f2, round to the type of t.
   r = t + d;     // This should produce the same overall result 
                  // regardless whether x87 stack or SSE/SSE2 is used.

controlfp does not change the MXCSR control bits. Therefore, with /arch:SSE2, any functionality that depends on using controlfp will be broken.

To set this compiler option for SSE or SSE2 in Visual Studio

  1. Open the Property Pages dialog box for the project. For more information, see How to: Open Project Property Pages.

  2. Click the C/C++ folder.

  3. Click the Code Generation property page.

  4. Modify the Enable Enhanced Instruction Set property.

To set the /arch:AVX compiler option in Visual Studio

  1. Open the Property Pages dialog box for the project. For more information, see How to: Open Project Property Pages.

  2. Click the C/C++ folder.

  3. Click the Command Line property page.

  4. In the Additional options box, add /arch:AVX.

To set this compiler option programmatically

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